/******************************************************************************
*
* MODULE:    Receptor_Asc_TB.v
* DEVICE:     Test Bench
* PROJECT:   Tarea 1 Diseño Electronico Digital
* AUTHOR:    Ricardo Dávila Castro   
* DATE:      2010 16:18:23
*
* ABSTRACT:  Test Bench Receptor serial ascincrono Ejercicio Dos
*            
*******************************************************************************/
`timescale 1ns / 100ps

`ifndef 	RECEPTOR_ASC_TB
`define    RECEPTOR_ASC_TB

module Receptor_Asc_TB();
reg data_in;
reg clk;
reg en;
initial begin
clk = 1'b0;
forever #10.5 clk = ~clk;
end
initial
begin
	en = 0;
	en= ~en;
	data_in = 1'b0;
	#5 data_in = ~data_in; 
	#10 data_in = ~data_in; 
	#20 data_in = ~data_in; 
	#10 data_in = ~data_in; 
	#10 data_in = ~data_in; 
	#10 data_in = ~data_in; 
	#10 data_in = ~data_in; 
	#10 data_in = ~data_in; 
	#20 data_in = ~data_in; 
end
Receptor_Asc instReceptor_Asc(.serial_in(data_in),.clk(clk),.en(en));
endmodule
`endif
